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Definition A machine consisting of a set of states, a start state, an input, and a transition function that maps input and current states to a next state. Machine begins in the start state with an input. It changes to new states depending on the transition function. The transition function depends on current states and inputs. The output of the machine depends on input and/or current state. There are two types of FSMs which are popularly used in the digital design. They are Moore machine Mealy machine Moore machine In Moore machine the output depends only on current state.The advantage of the Moore model is a simplification of the behavior. Mealy machine In Mealy machine the output depend on both current state and input.The advantage of the Mealy model is that it may lead to reduction of the number of states. In both models the next state depends on current state and input. Some times designers use mixed models. States will be encoded for representing a particular state. Representatio

Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv

1. Why are program counter and stack pointer 16-bit registers? Answer Program Counter (PC) and Stack Pointer (SP) are basically used to hold 16-bit memory addresses.PC stores the 16-bit memory address of the next instruction to be fetched. SP stores address of stack's starting block. 2. What happens during DMA transfer? Answer During DMA transfers DMA controller takes control of the data transfer, and the processor will carry out other tasks. 3. Define ISR. Answer An interrupt handler, also known as an interrupt service routine (ISR), is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt. Whenever there is an interrupt the processor jumps to ISR and executes it. 4. Define PSW. Answer The Program Status Word (PSW) is a register which contains information about the current program status used by the operating system and the underlying hardware. The PSW includes the instruction address, condition code, and other

System-on-a-chip (SoC) refers to integrating all components of an electronic system into a single integrated circuit (chip). A SoC can include the integration of: Ready made sub-circuits (IP) One or more microcontroller, microprocessor or DSP core(s) Memory components Sensors Digital, Analog, or Mixed signal components Timing sources, like oscillators and phase-locked loops Voltage regulators and power management circuits The blocks of SoC are connected by a special bus, such as the AMBA bus. DMA controllers are used for routing the data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC. SoC is widely used in the area of embedded systems. SoCs can be fabricated by several technologies, like, Full custom, Standard cell, FPGA, etc. SoC designs are usually power and cost effective, and more reliable than the corresponding multi-chip systems. A programmable SoC is known as PSoC. Advantages of SoC are: Small

1. Why is NAND gate preferred over NOR gate for fabrication? Answer NAND is a better gate for design than NOR because at the transistor level the mobility of electrons of NAND is normally three times that of holes compared to NOR and thus the NAND is a faster gate. The gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND (the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance PMOSs are in series connection which again increases the resistance). 2. Which transistor has higher gain: BJT or MOSFET and why? Answer BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law. 3. Why PMOS and NMOS are sized equally in a transmission gates? Answer In transmission gate, PMOS and NMOS aid each other rather than competing with each ot

A complex programmable logic device (CPLD) is a semiconductor device containing programmable blocks called macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. CPLD has complexity between that of PALs and FPGA s. It can has up to about 10,000 gates. CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications. Applications CPLDs are ideal for critical, high-performance control applications. CPLD can be used for digital designs which perform boot loader functions. CPLD is used to load configuration data for an FPGA from non-volatile memory. CPLD are generally used for small designs, for example, they are used in simple applications such as address decoding. CPLDs are often used in cost-sensitive, battery-operated portable applications, because of its small size and low-power usage. Architecture A CPLD contains a bunch of programmable functional blocks (FB) whose inputs an

>> Introduction >> Binary Number System >> Complements >> 2's Complement vs 1's Complement >> Binary Logic >> Logic Gates Introduction The fundamental idea of digital systems is to represent data in discrete form (Binary: ones and zeros) and processing that information. Digital systems have led to many scientific and technological advancements. Calculators, computers, are the examples of digital systems, which are widely used for commercial and business data processing. The most important property of a digital system is its ability to follow a sequence of steps to perform a task called program, which does the required data processing. The following diagram shows how a typical digital system will look like. Representing the data in ones and zeros, i.e. in binary system is the root of the digital systems. All the digital system store data in binary format. Hence it is very important to know about binary number system. Which is explained below.

1. What is the size of flag register of 8086 processor? Answer 16-bit. 2. How many pin IC 8086 is? Answer 40 pin dual in-line package. 3. What is the Maximum clock frequency of 8086? Answer 5 Mhz is the Maximum clock frequency of 8086. 4. What is meant by instruction cycle? Answer An instruction cycle also known as fetch-and-execute cycle and fetch-decode-execute cycle, is the time period during which a computer reads and processes a machine language instruction from its memory. 5. What is Von Neumann architecture? Answer The Von Neumann architecture is a computer design model that uses a processing unit and a single separate storage structure to hold both instructions and data. The instruction/data is read from storage and executed by the processing unit. It is also known as "stored-program computer". 6. What is the main difference between 8086 and 8085? Answer 8086 is 16-bit microprocessor, where as 8085 is a 8-bit microprocessor. 7. What does EAX mean? Answer With t

1. How many bits processor is 8086? Answer 16-bit processor. 2. What are the sizes of data bus and address bus in 8086? Answer 16-bit data bus, and 20-bit address bus. 3. What is the maximum addressable memory of 8086? Answer 1MByte, because 20-bit address bus. 4. How are 32-bit addresses stored in 8086? Answer 32-bit addresses are stored in "SEGMENT:OFFSET" format. SEGMENT and OFFSET are 16-bit values. ADDRESS = (SEGMENT* 16) + OFFSET 5. What are the 16-bit registers that are available in 8086? Answer The following are the 16-bit registers that are available in 8086. 8 general purpose registers: AX - Accumulator Register Bx - Base Register CX - Count Register DX - Data Register SP - Stack Pointer BP - Base Pointer SI - Source Index DI - Destination Index 4 segment registers: CS - Code Segment DS - Data Segment SS - Stack Segment ES - Extra Segment Others: IP - Instruction Pointer Flag register 6. What are the different types of address modes available in 8086? Answer Imp

1. Expand the following: PLA, PAL, CPLD, FPGA. Answer PLA - Programmable Logic Array PAL - Programmable Array Logic CPLD - Complex Programmable Logic Device FPGA - Field-Programmable Gate Array 2. Implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C using a PLA. Answer 3. What are PLA and PAL? Give the differences between them. Answer      Programmable Logic Array is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output.      PAL is programmable array logic, like PLA, it also has a wide, programmable AND plane. Unlike a PLA, the OR plane is fixed, limiting the number of terms that can be ORed together.      Due to fixed OR plane PAL allows extra space, which is used for other basic logic devices, such as multiplexers, exclusive-ORs, and latches. Most importantly, clocked elements

In Digital design, we often use a device to perform multiple applications. The device configuration is changed (reconfigured) by programming it. Such devices are known as programmable devices. It is used to build reconfigurable digital circuits. The following are the popular programmable device PLA - Programmable Logic Array PAL - Programmable Array Logic CPLD - Complex Programmable Logic Device ( Click here for more details) FPGA - Field-Programmable Gate Array ( Click here for more details) PLA: Programmable Logic Array is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products canonical forms. Suppose we need to implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C . The follo

Definitions FPGA : A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. For complete details click here . ASIC : An application-specific integrated circuit (ASIC) is an integrated circuit designed for a particular use, rather than intended for general-purpose use. Processors, RAM, ROM, etc are examples of ASICs. FPGA vs ASIC Speed ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can be optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have hight speed clocks. Cost FPGAs are cost effective for small applications. But when it comes to complex and large volume designs (like 32-bit processors) ASIC products are cheaper. Size/A

A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Applications ASIC prototyping: Due to high cost of ASIC chips, the logic of the application is first verified by dumping HDL code in a FPGA. This helps for faster and cheaper testing. Once the logic is verified then they are made into ASICs. Very useful in applications that can make use of the massive parallelism offered by their architecture. Example: code breaking, in particular brute-force attack, of cryptographic algorithms. FPGAs are sued for computational kernels such as FFT or Convolution instead of a micr

Random Access Memory (RAM) is a type of computer data storage. Its mainly used as main memory of a computer. RAM allows to access the data in any order, i.e random. The word random thus refers to the fact that any piece of data can be returned in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data. You can access any memory cell directly if you know the row and column that intersect at that cell.     Most of the RAM chips are volatile types of memory, where the information is lost after the power is switched off. There are some non-volatile types such as, ROM, NOR-Flash. SRAM: Static Random Access Memory SRAM is static, which doesn't need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. SRAM is volatile memory. Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two a

Direct memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Principle of DMA DMA is an essential feature of all modern computers, as it allows devices to transfer data without subjecting the CPU to a heavy overhead. Otherwise, the CPU would have to copy each piece of data from the source to the destination. This is typically slower than copying normal blocks of memory since access to I/O devices over a peripheral bus is generally slower than normal system RAM. During this time the CPU would be unavailable for any other tasks involving CPU bus access, although it could continue doing any work which did not require bus access. A DMA transfer essentially copies a block of memory from one device to an

Digital Design Interview Questions - 1 Digital Design Interview Questions - 2 Digital Design Interview Questions - 3 Digital Design Interview Questions - 4 Digital Design Interview Questions - 5 Microprocessor Interview Questions - 1 Microprocessor Interview Questions - 2 Microprocessor Interview Questions - 3 Microprocessor Interview Questions - 4 Verilog Interview Questions - 1 Verilog Interview Questions - 2 Verilog Interview Questions - 3 VLSI Interview Questions - 1 VLSI Interview Questions - 2 VLSI Interview Questions - 3 VLSI Interview Questions - 4 VLSI Interview Questions - 5 Introduction to Digital Logic Design Introduction Mealy and Moore FSMs One-hot Encoding Introduction to Verilog HDL Basics: Lexical Tokens Basics: Data Types Modules Ports List Of Operators Gate-Level Modeling Dataflow Modeling Behavioral Modeling Tasks and Functions The VLSI Design Flow Complex Programmable Logic Device Direct Memory Access Field-Programmable Gate Array FPGA vs ASIC Parallel vs Seri

Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time. The setup time is the interval before the clock where the data must be held stable. The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time. In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the h

Parallel and serial data transmission are most widely used data transfer techniques. Parallel transfer have been the preferred way for transfer data. But with serial data transmission we can achieve high speed and with some other advantages. In parallel transmission n bits are transfered simultaneously, hence we have to process each bit separately and line up them in an order at the receiver. Hence we have to convert parallel to serial form. This is known as overhead in parallel transmission. Signal skewing is the another problem with parallel data transmission. In the parallel communication, n bits leave at a time, but may not be received at the receiver at the same time, some may reach late than others. To overcome this problem, receiving end has to synchronize with the transmitter and must wait until all the bits are received. The greater the skew the greater the delay, if delay is increased that effects the speed. Another problem associated with parallel transmission is crosstalk.

1. Design 2 input AND, OR, and EXOR gates using 2 input NAND gate. Answer 2. Design a circuit which doubles the frequency of a given input clock signal. Answer 3. Implement a D-latch using 2x1 multiplexer(s). Answer 4. Give the excitation table of a JK flip-flop. Answer 5. Give the Binary, Hexadecimal, BCD, and Excess-3 code for decimal 14. Answer 14: Binary: 1110 Hexadecimal: E BCD: 0001 0100 Excess-3: 10001 6. What is race condition? Answer 7. Give 1's and 2's complement of 19. Answer 19: 10011 1's complement: 01100 2's complement: 01101 8. Design a 3:6 decoder. Answer 9. If A*B=C and C*A=B then, what is the Boolean operator * ? Answer * is Exclusive-OR. 10. Design a 3 bit Gray Counter. Answer

1. How are blocking and non-blocking statements executed? Answer In a blocking statement, the RHS will be evaluated and the LHS will be then updated, without interruption from any other Verilog statement. A blocking statement "blocks" trailing statements. In a non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the LHS will be updated at the end of the time step. 2. How do you model a synchronous and asynchronous reset in Verilog? Answer Synchronous reset: always @( posedge clk) begin -- if (reset) -- end Asynchronous reset: always @( posedge clk or posedge reset) begin -- if (reset) -- end The logic is very simple: In asynchronous reset, the always block will invoked at positive edge of the reset signal, irrespective of clock's value. 3. What happens if there is connecting wires width mismatch? Answer For example there are two signals rhs[7:0], and lhs[15:0]. If we do rhs = lhs. Then it is equivalent to rhs = lhs[7:0]. Assignm

This sections contains interview questions related to LOW POWER VLSI DESIGN. 1. What are the important aspects of VLSI optimization? Answer Power, Area, and Speed. 2. What are the sources of power dissipation? Answer + Dynamic power consumption, due to logic transitions causing logic gates to charge/discharge load capacitance. + Short-circuit current, this occurs when p-tree and n-tree shorted (for a while) during logic transition. + Leakage current, this is a very important source of power dissipation in nano technology, it increases with decrease in lambda value. It is caused due to diode leakages around transistors and n-wells. 3. What is the need for power reduction? Answer Low power increases noise immunity, increases batter life, decreases cooling and packaging costs. 4. Give some low power design techniques. Answer Voltage scaling, transistor resizing, pipelining and parallelism, power management modes like standby modes, etc. 5. Give a disadvantage o